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Commits on Aug 13, 2020

• Update README.md

  kyaso

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Commits on Aug 2, 2020

• Update README.md

  kyaso

  authored
  2ddb53b

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Commits on Jul 25, 2020

• Add README

  kyaso

  committed
  566d4b7

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Commits on Nov 2, 2019

• Improve Make

  kyaso

  committed
  0d1c0f6

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Commits on Oct 29, 2019

• Fibonacci works on FPGA!

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  kyaso

  committed
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Commits on Sep 22, 2019

• Improved Makefile

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  kyaso

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• Added Fibonacci test

  kyaso

  committed
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Commits on Sep 18, 2019

• Fixed byte ordering to little endian

  kyaso

  committed
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Commits on Sep 17, 2019

• Added python script which generates tcl script from binary

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  kyaso

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Commits on Sep 16, 2019

• Added target to generate raw binary

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  kyaso

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Commits on Sep 14, 2019

• Started adding some software tests

  kyaso

  committed
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Commits on Sep 4, 2019

• Added chip enable signal for RAM

  kyaso

  committed
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Commits on Sep 1, 2019

• Added PC output port to top module (for debugging)

  kyaso

  committed
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• Improved testbenches

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  kyaso

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Commits on Aug 31, 2019

• Fixed some port issues which occurred during Vivado synthesis

  kyaso

  committed
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Commits on Aug 29, 2019

• Added some folders to gitignore

  kyaso

  committed
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Commits on Aug 24, 2019

• Added test case for FENCE

  kyaso

  committed
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Commits on Aug 18, 2019

• Connected RAM to CPU. Verified

  kyaso

  committed
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• Added HALT signal

  kyaso

  committed
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• Added test for branch. Seems to work

  kyaso

  committed
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• Fixed next PC logic

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  kyaso

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Commits on Aug 17, 2019

• Started implementing and verifying CPU top. First test successful

  kyaso

  committed
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• Verified EXECUTE unit

  kyaso

  committed
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• EXECUTE: Added ALU, fixed some signals

  kyaso

  committed
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Commits on Aug 14, 2019

• Fixed comparison process

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  kyaso

  committed
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Commits on Aug 13, 2019

• Testbench for ALU; ALU has issues with signed compares currently

  kyaso

  committed
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• Moved ALU to separate file

  kyaso

  committed
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Commits on Aug 12, 2019

• Started implementing Execute Unit

  kyaso

  committed
  b37e09d

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• Outputs which are assigned value in procedural statement need to be reg

  kyaso

  committed
  f074026

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• Decoder: Split up jalr into jal and jalr

  kyaso

  committed
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• First version of Decoder

  kyaso

  committed
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Commits on Aug 11, 2019

• First version of bitselect

  kyaso

  committed
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• RAM: Added support for different word lengths

  kyaso

  committed
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Commits on Aug 10, 2019

• Implemented first version of Regfile. Tested in Verilator

  kyaso

  committed
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• Implemented first version of RAM. Tested in Verilator

  kyaso

  committed
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