It is not an issue in fact, but I wandered how to support hardware ECC, maybe some changes should be a better way to support HW ECC.

Current source code logic in fs_dev_nand_ctrlr_gen.c:SecWr,

1. write sector data
2. calculate ECC of sector + OOS data (p_ctrlr_data->CtrlrExtPtr->ECC_Calc)
3. SparePack OOS data
4. write OOS to OOB (ECC included after OOS)

I suppose the following process can be followed to support HW ECC:

1. write sector data
2. SparePack OOS data
3. write OOS to OOB
4. p_ctrlr_data->CtrlrExtPtr->ECC_Calc
   in this callback function, get ECC from HW like STM32 MCU FSMC register (it calculates ECC for each certain bytes data written)
5. write ECC to OOB

With these changes, both software ECC and HW ECC can be supported.

I don't know if it makes sense. Thanks!