Pinned Loading

1. vip_amba_apb_ms_uvm vip_amba_apb_ms_uvm Public

   UVM based Verification IP for the AMBA APB protocol. ( Supports both master & slave )

   SystemVerilog 1

2. ip_amba_ahb_ms_rtl_v ip_amba_ahb_ms_rtl_v Public

   RTL design for the AMBA AHB protocol.

   SystemVerilog 8 3

3. ip_amba_apb_ms_rtl_v ip_amba_apb_ms_rtl_v Public

   The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )

   Verilog 15 5

4. ip_parallel_custom_crc_gerator_verilog ip_parallel_custom_crc_gerator_verilog Public

   Verilog parallel CRC generation module with custom polynomial and variable width

   Perl 5 2

5. rtl_template_gen rtl_template_gen Public

   Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )

   Shell 3

6. std_module std_module Public

   All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

   Verilog 3 1